Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder
نویسندگان
چکیده
In this paper, we present an implementation of a turbo product codes (TPC) decoder achieved on a novel Reconfigurable Multimedia Accelerator (RMA). The RMA is based on the principle of hierarchical shared memory storage managed through a dedicated local controller favoring high data throughput, while squeezing round-trip memory latencies. The mapping methodology facilitates the characterization of the RMA for a TPC decoder in terms of the communication and computation resources.
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